This invention relates to the field of digital data acquisition, and more particularly to the field of the identification of unstable intervals in dual threshold synchronous data.
For each family of digital logic devices, there is a voltage level above which the signal is unambiguously high and another voltage level below which the signal is unambiguously low, but there is also a zone in-between these two voltage levels that is neither unambiguously high nor unambiguously low. Normally, the voltage level of the signal only passes through this in-between region during logical transitions from high to low or low to high, although glitches or severe noise on the signal may result in unintended excursions into this region Data whose voltage level is within this in-between region may be considered to be "unstable", since it is neither high nor low and is likely to be making a transition between these two logic states. Conversely, data which is one of the well defined states of high or low may be considered to be "stable".
Setup and hold time specifications inform the designer considering a particular logic device how much time, relative to the time of occurrence of a clock signal active edge, the device needs to have the signal at its input in a stable condition before and after the active clock edge. Setup time is the minimum time that an input signal must be stable prior to the active clock edge, while hold time is the minimum time that the signal must remain stable after the active clock edge. If either of these conditions are violated, the device is not guaranteed to perform its function properly.
A variety of modern digital instruments acquire data from synchronous systems and therefore would be improved by having a way of knowing when setup and hold requirements are violated. These include such instruments as logic analyzers, microprocessor analyzers, emulators, and integrated circuit testers. One prior art logic analyzer, the DAS 9200 Digital Analysis System from Tektronix, Inc., is known to include a module, the 92A16 Data Acquisition Module, that permits setup and hold violation monitoring. This module does not, however, actually measure when the data is between logic levels, but rather relies on glitch detection and high speed asynchronous monitoring of the data to detect transitions. As shown in FIG. 1, detected edges and glitches are ORed to create a bit-unstable signal for each channel. These are then ORed across all of the channels of interest to a bus-unstable signal. The setup and hold times are then measured with respect to this unstable signal.
Recognition of unstable asynchronous data is not new. FIG. 2 shows a prior art circuit suitable for recognizing when asynchronous data is unstable. Two voltage comparators compare the level of a single digital data signal to a high threshold and a low threshold. An AND gate connected to the outputs of the two comparators detects when the signal is above the low threshold and below the high threshold, generating an in-between signal when this occurs. The in-between signals for a set of related signals are ORed to produce an unstable signal that indicates when any of the signals in the set are in-between.
However, when acquisition probes are employed which synchronize the incoming data from dual thresholds to the system clock in the probe, and this synchronized data is then transmitted through a cable to the actual acquisition instrument, the circuitry in that instrument must be able to recognize the occurrence of unstable data in this dual threshold synchronous data. What is desired is a circuit that allows digital data acquisition instruments to recognize when dual threshold synchronous data being monitored is unstable.